Memory devices provide data storage for electronic systems. One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that may be erased and reprogrammed in blocks. Many modern personal computers have BIOS stored on a flash memory chip. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of non-volatile memory cells arranged in row and column fashion. The cells are usually grouped into blocks. Each of the cells within a block may be electrically programmed by charging a floating gate. The charge may be removed from the floating gate by a block erase operation. Data is stored in a cell as charge in the floating gate.
NAND is a basic architecture of flash memory. A NAND cell unit comprises at least one select gate coupled in series to a serial combination of memory cells (with the serial combination being commonly referred to as a NAND string). The gates of the NAND string have traditionally been single level cells (SLCs), but manufacturers are transitioning to utilization of multilevel cells (MLCs) for gates of NAND strings. An SLC stores only one data bit, whereas an MLC stores multiple data bits. Accordingly, memory array density can be at least doubled by transitioning from SLCs to MLCs.
MLCs differ from SLCs in the programming of the devices. Specifically, a device may be programmed as an SLC if the device is programmed to have only two memory states (0 or 1), with one of the memory states corresponding to one level of stored charge at a floating gate (for example, corresponding to the fully charged device) and the other corresponding to another level of stored charge at the floating gate (for example, corresponding to the fully discharged device). Alternatively, the device may be programmed as an MLC having two bits of memory if the device is programmed to have four memory states. The memory states may be designated as the 11, 01, 00, and 10 memory states, in order from lowest stored charge (for example, fully discharged) to highest stored charge (for example, fully charged). Accordingly, the 11 state corresponds to a lowest stored charge state, the 10 state corresponds to a highest stored charge state, and the 01 and 00 states correspond to, for example, first and second intermediate levels of stored charge.
Regardless of whether devices are utilized as MLCs or SLCs, there are continuing goals to avoid parasitic capacitive coupling effects and stress-induced gate leakage, and to have a large memory window (with a memory window being the charge window that enables a non-volatile cell to be charged, and being defined by how much charge is placed on the cell within a given time). A large memory window may enable the multiple memory states of an MLC device to be clearly separated from one another.
Charge-trapping materials, such as, for example, metallic charge traps (MCTs) show promise for utilization in non-volatile memory cells, but difficulties are presented in obtaining large memory windows, good retention of charge by non-volatile devices, and uniformity across numerous devices of a NAND array (in other words, avoiding cell-to-cell sigma variation).
It is desired to develop structures and fabrication processes by which to alleviate or overcome one or more of the above-discussed difficulties and/or to achieve one or more of the above-discussed goals.